Related Art: Unless expressly identified as being publicly or well known, mention herein of techniques and concepts, including for context, definitions, or comparison purposes, should not be construed as an admission that such techniques and concepts are previously publicly known or otherwise part of the prior art. All references cited herein (if any), including patents, patent applications, and publications, are hereby incorporated by reference in their entireties, whether specifically incorporated or not, for all purposes.
Various aspects of flash memory as used by Solid State Disk (SSD) controllers will now be described in part to establish a technology background and in part to establish antecedents for nomenclature used in the balance of the specification. The minimal size of data readable by the SSD controller from Non-Volatile Memory (NVM) is a “read unit” that is protected by included error correction, such as a Low-Density Parity-Check (LDPC) code. In some contexts, a read unit is referred to as a “codeword”. In some embodiments, each read unit contains approximately 4K to approximately 32K bits of user data, plus error correction overhead. Under command of the SSD controller, those bits are read from NVM memory cells (e.g., via an array access of one or more portions of the NVM memory cells), which depending on the technology as discussed below, may hold one or more bits per cell. In some embodiments, for security reasons an SSD controller encrypts the data prior to writing the data to NVM. In some embodiments, in view of circuit design limitations with respect to long strings of identically programmed cells, an SSD controller scrambles the data prior to writing the data to NVM.
Considered individually, each cell has a particular stored (programmed) charge that corresponds to a device threshold voltage for that cell, and further corresponds to the logical bit values being stored in the cell. While ideally all of the cells in the NVM would have identical device threshold voltages for the logical bit values stored, in practice for a variety of reasons the device threshold voltages differ across the cells in probability distributions along the device threshold voltage axis (e.g., “device threshold voltage distributions”) that are similar to a Gaussian in shape.
Thus, considered in aggregate across a large number of cells, such as of a read unit, there are as many device threshold voltage distributions (e.g., Gaussian probability curves) as there are states per cell (two states per bit of storage per cell). That is, for N-bits per cell of storage, there are 2N states and the same number of device threshold voltage distributions. Generally, (2N)−1 different read thresholds (read reference voltages VREAD1 through VREADN−1) are required by read circuits in the NVM to distinguish between the 2N states.
Continuing from above, for Single-Level Cell (SLC) flash memories, N=1. SLC memories thus store one-bit per cell of storage, have two device threshold voltage distributions (one for zeroes and another for ones), and require a single read threshold, read reference voltage VREAD1. From lower to higher device threshold voltages, the two device threshold voltage distributions are known as the E (Erased) state and D1 (first Data) state. While arbitrary, a common mapping (coding) is to assign logical one to the E state and logical zero to the D1 state. Thus, references to zeroes and ones are proxy references for respective decodings of the D1 state and the E state.
Continuing further from above, for Multi-Level Cell (MLC) flash memories, N>1. MLC memories thus store more than one bit per cell, have more than two device threshold voltage distributions, and require multiple different read thresholds to distinguish the distributions. For example, a 4LC memory (e.g., flash memory) stores two bits per cell, has four device threshold voltage distributions, and generally requires three read thresholds (read reference voltages VREAD1, VREAD2, and VREAD3). From lower to higher device threshold voltages, the four device threshold voltage distributions are known as the E (Erased), D1 (Data1), D2 (Data2), and D3 (Data3) states. While arbitrary, each of the four device threshold voltage distributions is also mapped (addressed) in accordance with a particular binary sequence, such as a Gray code sequence. Thus, references to one or more of the 11, 10, 00, and 01 states, are proxy references for respective decodings of the E, D1, D2, and D3 states.
With respect to address mapping used for the states of an MLC, each can be said to have a Most Significant Bit (MSB) and a Least Significant Bit (LSB) (and for more than two bits per cell, bits of significance in between). While there are various ways that MLC NVMs program their cells, the following approach is common. An initial programming round (a manipulation of the charge distributions) establishes the LSB, e.g., writes the “lower pages”. This is done loosely in the same manner as for writing an SLC, e.g., a charge manipulation that establishes the E state device threshold voltage distribution and a second state device threshold voltage distribution. Depending on the binary sequence used, the second state device threshold voltage distribution is similar to the D1 state device threshold voltage distribution, similar to the D2 state device threshold voltage distribution, or between the D1 and D2 state device threshold voltage distributions. For MLC, one or more additional programming rounds further manipulate the device threshold voltage distributions (in number, location along the device threshold voltage axis, and in shape), as required per the number of levels of the MLC. More particularly, one or more subsequent programming operations write the “middle pages” (if any, for more than two bits per cell), and a last programming operation establishes the MSB, e.g., writes the “upper pages”. For example in a 4LC (2-bit per cell MLC), the E distribution and the second distribution of the first program round are respectively bifurcated by a second program round into E and D1 distributions and D2 and D3 distributions.
The device threshold voltage distributions are modified away from their initial/nominal distributions by one or more factors, such as read disturb, write disturb, and retention loss. More particularly, over time, temperature, and other factors related to use, the location of each of the device threshold voltage distribution can move around with respect to the device threshold voltage axis. Such changes increase the likelihood of read errors that are performed using a read reference voltage value for the read threshold that was previously established based on the nominal device threshold voltage distribution. In some SLC embodiments, when a hard-decision uncorrectable error is encountered in a read unit read from NVM, a series of retry operations is performed to recover the read unit. The retry operations include the controller re-reading the read unit at different read reference voltage values for VREAD1, such as determined by a register setting written via an I/O command from the SSD controller. By reading at different settings of the read reference voltage values, the read unit is sampled at different points on the device threshold voltage axis in an attempt to locate a sample of the read unit that is (hard-decision) correctable.
One algorithm suggested by NVM vendors involves sweeping the SLC read threshold slowly upwards (increasing the read reference voltage VREAD1 from its nominal value) in an attempt to find a sample of the read unit that is correctable. If this procedure fails, then the read threshold is swept in another direction (decreasing the read reference voltage VREAD1 from its nominal value). If both sweeps fail, then the read unit is uncorrectable (by hard-decision decoding). Linearly sweeping the read threshold, which might have 16 to 64 steps at different respective read reference voltage settings, requires many time-consuming samples of the read unit (each with an attendant recovery time latency). Even when such a search is infrequently required, and thus not a major impact on average latencies, for applications with strict maximum latency requirements, including some database applications, such a time-consuming search is unacceptable.
Also, the adjustments that are made to the read reference voltage during the retry operations cannot be made on the fly at read time due to the latency that is involved with the process of sweeping the read reference voltage values. The sweeping process can only be performed when the extra time needed to perform it is not a major concern. Furthermore, while flash memory vendors provide the capability of adjusting the read reference voltages on a die level or chip enable (CE) level, there is no provision for separately setting the read reference voltages of different blocks within the same die. Often times it is necessary or desirable to be able to set the read reference voltages to different values for different blocks within the same die.
FIG. 1 is a block diagram of a portion of a flash memory configured as a Redundant Array of Independent Silicon Elements (RAISE™). In RAISE™ technology, data is duplicated across blocks of multiple dies, commonly referred to as R-blocks, to provide data redundancy that enables data to be recovered in the event of a die failure similar to the way in which Redundant Arrays of Independent Disks (RAID) technology duplicates data over multiple disks of a disk drive array to allow data to be recovered in the event of a disk failure. For example, as shown in FIG. 1, R-block 0 of R-blocks 0-M−1 includes blocks in Dies 0-N−1, wherein M and N are integers that are equal to or greater than one. In such a configuration, if a read in a block belonging to one R-block of one of the dies is being followed by a read in a block of a different R-block of the same die, the read that occurred earlier in time can necessitate an adjustment to the read reference voltages of the R-block that will be read later in time. For example, if a read in Block 0 of R-block 0 of Die 0 is followed by a read of Block 0 of R-block 2 of Die 0, the read of Block 0 of R-block 0 can affect the device threshold voltage distributions of cells of Block 0 of R-block 2 in a way that necessitates an adjustment to the read reference voltages of R-block 2 before the subsequent read of R-block 2 occurs.
However, adjusting the read reference voltage values this frequently may result in a significant read performance penalty due to the latency associated with making these adjustments. For example, for an upper page read in MLC flash, up to two reference voltage values may need to be adjusted. For an upper page read in TLC flash, the read performance penalty may be even worse because up to four read reference voltage values may need to be adjusted. Accordingly, a need exists for a way to reduce or eliminate the read performance penalty associated with adjusting the read reference voltages.